1. Field of the Invention
The invention relates generally to testing systems for electronic components and, more particularly, to a method and an apparatus for determining the failing operation of a device-under-test (DUT).
2. Description of Related Art
Testing of hardware and software generally involves executing a set of instructions and/or commands and comparing the actual results with the expected results. If the actual results match the expected results, the test case was successful. If the actual results do not match the expected results, then the test case failed.
Generally, determining where in the failed test case that the failure actually occurred, i.e., the failed instruction, is a manual process. One technique of determining the failed instruction utilizes a pattern generator to reconfigure the DUT to a repeatable starting state, allowing for a repeatable instruction stream. This technique, however, is limited to the number of instructions generated by the pattern generator.
Another technique, commonly utilized in situations where the instructions comprise a set of uncontrollable source code, such as an operating system boot sequence, is to configure a host computer to halt the DUT at various cycles. The state of the DUT is evaluated and compared to the state of a known, good device in a similar state.
These techniques, however, are generally time consuming and complicated. The results and or the state of the DUT is not always readily available or apparent and may require additional analysis.
Therefore, there is a need to provide a method and an apparatus to automatically test a DUT and to identify the failing instruction.